MindCrea Ltd

ProTimingTM is Prolific’s block level timing and power optimization tool, giving the IC designers up to 20% improvement.  ProTiming does not change RTL, and automatically feeds the information on the changes effecting to the cells to be used, to P&R ECO.

ProPowerTM reduces the leakage power up to 25% by the optimizing away the excessive low VT transistors in the designs.  A percentage of 10% in low  VT  transistors of all transistors ión the chip can reduce leakage up to 40%.



EVE is the leader in Hardware/Software Co-Verification.  Nine of the top 10 semiconductor companies rely on ZeBu to verify their SOCs. With the best ROI on the market, ZeBu is also the choice of startups that need first-pass silicon success.

EVE also has specific solutions for SOCs based on embedded processor models like Tensilica Diamond.  EVE also offers a wide range of validation IP so you can easily and quickly build complex test environments and platforms.  EVE offers tools to write custom transactor Bus Functional Models to speed-up the emulation.

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In the IC design rule world, there can be a conflict in between minimizing the area and achieving a high yield through using wider design rules.  This is because the design for manufacturability and resolution enhancement technologies often require geometries beyond what a strictly minimum-area focus would allow.  In the picture above the polysilicon gate has been extended near the diffusion to improve the yield.  In some processes this has even been made a rule.


Please read the article “Improving yields without compromising area” , by Paul de Dood in the EEdesign magazine, August 13, 2004.